IDT70V9359 Datasheet, PDF (1/16 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V 8/4K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT70V9359/49L
Features:
◆ _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed clock to data access}
– Commercial: 6.5/7.5/9ns (max.)
– Industrial: 7.5ns (max.)
◆ _{Low-power operation}
– IDT70V9359/49L
Active: 450mW (typ.)
Standby: 1.5mW (typ.)
◆ _{Flow-Through or Pipelined output mode on either port via}
the FT/PIPE pins
◆ _{Counter enable and reset features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
Functional Block Diagram
◆ _{Full synchronous operation on both ports}
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
◆ _{Separate upper-byte and lower-byte controls for}
multiplexed bus and bus matching compatibility
◆ _{LVTTL- compatible, single 3.3V (±0.3V) power supply}
◆ _{Industrial temperature range (–40°C to +85°C) is}
available for 83 MHz
◆ _{Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-}
pin Fine Pitch Ball Grid Array (fpBGA) packages.
R/WL
UBL
CE0L
CE1L
1
0
0/1
LBL
OEL
FT/PIPEL
I/O9L-I/O17L
I/O0L-I/O8L
A12L⁽¹⁾
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1 ^{1b 0b} b a ^{1a 0a}
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
1
0
0/1
0a 1a _{a b0b} 1b _0/1
Counter/
Address
Reg.
NOTE:
1. A12 is a NC for IDT70V9349.
R/WR
UBR
CE0R
CE1R
LBR
OER
FT/PIPER
I/O9R-I/O17R
I/O0R-I/O8R
A12R⁽¹⁾
A0R
CLKR
ADSR
CNTENR
CNTRSTR
5638 drw 01
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©2003 Integrated Device Technology, Inc.
AUGUST 2003
DSC-5638/3