IDT70V9289L Datasheet, PDF (1/15 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V 64K x 16
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
PRELIMINARY
IDT70V9289L
Features:
x _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
x _{High-speed clock to data access}
– Commercial: 7.5/9/12ns (max.)
x _{Low-power operation}
– IDT70V9289L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
x _{Flow-Through or Pipelined output mode on either port via}
the FT/PIPE pins
x _{Counter enable and reset features}
x _{Dual chip enables allow for depth expansion without}
additional logic
x _{Full synchronous operation on both ports}
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
x _{Separate upper-byte and lower-byte controls for}
multiplexed bus and bus matching compatibility
x _{LVTTL- compatible, single 3.3V (±0.3V) power supply}
x _{Industrial temperature range (–40°C to +85°C) is}
available for selected speeds
x _{Available in a 128-pin Thin Quad Flatpack (TQFP)}
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
1
0
0/1
LBL
OEL
FT/PIPEL
I/O8L-I/O15L
I/O0L-I/O7L
A15L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1
1b 0b
b
a ^{1a 0a}
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
R/WR
UBR
CE0R
1
0
CE1R
0/1
LBR
OER
0a 1a
a
b0b ^1b
0/1
Counter/
Address
Reg.
FT/PIPER
I/O8R-I/O15R
I/O0R-I/O7R
A15R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4855 drw 01
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©2000 Integrated Device Technology, Inc.
JUNE 2000
DSC-4855/1