IDT70V9179 Datasheet, PDF (1/15 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 32K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V 32K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
PRELIMINARY
IDT70V9179L
.eatures:
x _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
x _{High-speed clock to data access}
– Commercial: 7.5/9/12ns (max.)
Industrial: 9ns (max)
x _{Low-power operation}
– IDT70V9179L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
x _{Flow-Through or Pipelined output mode on either port via}
the FT/PIPE pins
x _{Counter enable and reset features}
x _{Dual chip enables allow for depth expansion without}
additional logic
x _{Full synchronous operation on both ports}
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
x _{LVTTL- compatible, single 3.3V (±0.3V) power supply}
x _{Industrial temperature range (–40°C to +85°C) is}
available for selected speeds
x _{Available in a 100-pin Thin Quad Flatpack (TQFP)}
.unctional Block Diagram
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1
CE1R
0
0/1
FT/PIPEL
I/O0L - I/O8L
A14L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1 ¹
0
I/O
Control
I/O
Control
0
1
0/1
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
FT/PIPER
I/O0R - I/O8R
A14R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
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©2002 Integrated Device Technology, Inc.
JANUARY 2002
DSC-5645/1