IDT70V7599S_09 Datasheet, PDF (1/22 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

HIGH-SPEED 3.3V 128K x 36
SYNCHRONOUS
BANK-SWITCHABLE
Š ^{DUAL-PORT STATIC RAM}
WITH 3.3V OR 2.5V INTERFACE
IDT70V7599S
Features:
◆ _{128K x 36 Synchronous Bank-Switchable Dual-ported}
SRAM Architecture
– 64 independent 2K x 36 banks
– 4 megabits of memory on chip
◆ _{Bank access controlled via bank address pins}
◆ _{High-speed data access}
– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
◆ _{Selectable Pipelined or Flow-Through output mode}
◆ _{Counter enable and repeat features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{Full synchronous operation on both ports}
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ _{Separate byte controls for multiplexed bus and bus}
matching compatibility
◆ _{LVTTL- compatible, 3.3V (±150mV) power supply}
for core
◆ _{LVTTL compatible, selectable 3.3V (±150mV) or 2.5V}
(±100mV) power supply for I/Os and control signals on
each port
◆ _{Industrial temperature range (-40°C to +85°C) is}
available at 166MHz and 133MHz
◆ _{Available in a 208-pin Plastic Quad Flatpack (PQFP),}
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
◆ _{Supports JTAG features compliant with IEEE 1149.1}
Functional Block Diagram
PL/FTL
OPTL
CLKL
ADSL
CNTENL
REPEATL
R/WL
CE0L
CE1L
BE3L
BE2L
BE1L
BE0L
OEL
CONTROL
LOGIC
I/O0L-35L
I/O
CONTROL
A10L
A0L
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
ADDRESS
DECODE
BANK
DECODE
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
©2009 Integrated Device Technology, Inc.
MUX
2Kx36
MEMORY
ARRAY
(BANK 0)
MUX
MUX
2Kx36
MEMORY
ARRAY
(BANK 1)
MUX
MUX
2Kx36
MEMORY
ARRAY
(BANK 63)
MUX
TDI
TDO
JTAG
1
TMS
TCK
TRST
CONTROL
LOGIC
I/O
CONTROL
PL/FTR
OPTR
CLKR
ADSR
CNTENR
REPEATR
R/WR
CE0R
CE1R
BE3R
BE2R
BE1R
BE0R
OER
I/O0R-35R
ADDRESS
DECODE
BANK
DECODE
A10R
A0R
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
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JANUARY 2009
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