IDT70V7519S Datasheet, PDF (1/22 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

HIGH-SPEED 3.3V 256K x 36
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V7519S
Features:
x _{256K x 36 Synchronous Bank-Switchable Dual-ported}
SRAM Architecture
– 64 independent 4K x 36 banks
– 9 megabits of memory on chip
x _{Bank access controlled via bank address pins}
x _{High-speed data access}
– Commercial: 3.4ns(200MHz)/3.6ns (166MHz)/4.2ns
(133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
x _{Selectable Pipelined or Flow-Through output mode}
x _{Counter enable and repeat features}
x _{Dual chip enables allow for depth expansion without}
additional logic
x _{Full synchronous operation on both ports}
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
x _{Separate byte controls for multiplexed bus and bus}
matching compatibility
x _{LVTTL- compatible, 3.3V (±150mV) power supply}
for core
x _{LVTTL compatible, selectable 3.3V (±150mV) or 2.5V}
(±100mV) power supply for I/Os and control signals on
each port
x _{Industrial temperature range (-40°C to +85°C) is}
available at 166MHz and 133MHz
x _{Available in a 208-pin Plastic Quad Flatpack (PQFP),}
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
x _{Supports JTAG features compliant with IEEE 1149.1}
Functional Block Diagram
PL/FTL
OPTL
CLKL
ADSL
CNTENL
REPEATL
R/WL
CE0L
CE1L
BE3L
BE2L
BE1L
BE0L
OEL
CONTROL
LOGIC
I/O0L-35L
I/O
CONTROL
A11L
A0L
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
ADDRESS
DECODE
BANK
DECODE
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
©2002 Integrated Device Technology, Inc.
MUX
4Kx36
MEMORY
ARRAY
(BANK 0)
MUX
MUX
4Kx36
MEMORY
ARRAY
(BANK 1)
MUX
TDI
TDO
MUX
4Kx36
MEMORY
ARRAY
(BANK 63)
MUX
JTAG
TMS
TCK
TRST
1
CONTROL
LOGIC
I/O
CONTROL
PL/FTR
OPTR
CLKR
ADSR
CNTENR
REPEATR
R/WR
CE0R
CE1R
BE3R
BE2R
BE1R
BE0R
OER
I/O0R-35R
ADDRESS
DECODE
BANK
DECODE
A11R
A0R
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
,
5618 drw 01
DECEMBER 2002
DSC 5618/5