IDT70V7339S_15 Datasheet, PDF (1/22 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V 512K x 18
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
Š _{WITH 3.3V OR 2.5V INTERFACE}
IDT70V7339S
Features:
◆ _{512K x 18 Synchronous Bank-Switchable Dual-ported SRAM}
Architecture
– 64 independent 8K x 18 banks
– 9 megabits of memory on chip
◆ _{Bank access controlled via bank address pins}
◆ _{High-speed data access}
– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
◆ _{Selectable Pipelined or Flow-Through output mode}
◆ _{Counter enable and repeat features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{Full synchronous operation on both ports}
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ _{Separate byte controls for multiplexed bus and bus match-}
ing compatibility
◆ _{LVTTL- compatible, 3.3V (±150mV) power supply}
for core
◆ _{LVTTL compatible, selectable 3.3V (±150mV) or 2.5V}
(±100mV) power supply for I/Os and control signals on each
port
◆ _{Industrial temperature range (-40°C to +85°C) is}
available at 166MHz and 133MHz
◆ _{Available in 208-pin fine pitch Ball Grid Array (fpBGA) and}
256-pin Ball Grid Array (BGA)
◆ _{Supports JTAG features compliant with IEEE 1149.1}
◆ _{Green parts available, see ordering information}
Functional Block Diagram
PL/FTL
OPTL
CLKL
ADSL
CNTENL
REPEATL
R/WL
CE0L
CE1L
UBL
LBL
OEL
CONTROL
LOGIC
I/O0L-17L
I/O
CONTROL
A12L
A0L
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
ADDRESS
DECODE
BANK
DECODE
NOTE:
1. TheBank-Switchabledual-portusesatrueSRAMcore
instead of the traditional dual-port SRAM core. As a result, it
has unique operating characteristics. Please refer to the
functional description on page 18 for details.
MUX
8Kx18
MEMORY
ARRAY
(BANK 0)
MUX
MUX
8Kx18
MEMORY
ARRAY
(BANK 1)
MUX
MUX
8Kx18
MEMORY
ARRAY
(BANK 63)
MUX
TDI
TDO
JTAG
TMS
TCK
TRST
1
©2015 Integrated Device Technology, Inc.
CONTROL
LOGIC
PL/FTR
OPTR
CLKR
ADSR
CNTENR
REPEATR
R/WR
CE0R
CE1R
UBR
LBR
OER
I/O
CONTROL
I/O0R-17R
ADDRESS
DECODE
BANK
DECODE
A12R
A0R
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
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