IDT70V657S Datasheet, PDF (1/23 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V 32K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
PRELIMINARY
IDT70V657S
Features
x _{True Dual-Port memory cells which allow simultaneous}
access of the same memory location
x _{High-speed access}
– Commercial: 10/12/15ns (max.)
– Industrial: 12/15ns (max.)
x _{Dual chip enables allow for depth expansion without}
external logic
x _{IDT70V657 easily expands data bus width to 72 bits or}
more using the Master/Slave select when cascading more
than one device
x _{M/S = VIH for BUSY output flag on Master,}
M/S = VIL for BUSY input on Slave
x _{Busy and Interrupt Flags}
x _{On-chip port arbitration logic}
x _{Full on-chip hardware support of semaphore signaling}
between ports
x _{Fully asynchronous operation from either port}
x _{Separate byte controls for multiplexed bus and bus}
matching compatibility
x _{Supports JTAG features compliant to IEEE 1149.1}
x _{LVTTL-compatible, single 3.3V (±150mV) power supply}
for core
x _{LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)}
power supply for I/Os and control signals on each port
x _{Available in 208-pin Plastic Quad Flatpack, 208-ball fine}
pitch Ball Grid Array and 256-ball Ball Grid Array
x _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
Functional Block Diagram
BE3L
BE2L
BE1L
BE0L
R/W L
CE0 L
CE1L
B BB
E EE
0 12
L LL
BB BB B
EE EE E
33 21 0
L R RR R
BE3R
BE2R
BE1R
BE0R
R/WR
CE0 R
CE1R
OE
L
I/O0L- I/O35L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
32K x 36
MEMORY
ARRAY
Di n_L
Di n_R
OE
R
I/O0R - I/O35R
A14 L
A0 L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A14R
A0R
BUSY_L
SEM_L
INT_L
CE 0 L
CE1L
OEL
R/WL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
TDI
TDO
JTAG
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
1
©2001 Integrated Device Technology, Inc.
OE_R
R/WR
CE0 _R
CE1R
TMS
TCK
TRST
BUSY_R
SEM_R
INT_R
5615 drw 01
JUNE 2001
DSC-5615/3