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IDT70V38L_15 Datasheet, PDF (1/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64K x 18 DUAL-PORT STATIC RAM | |||
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HIGH-SPEED 3.3V
64K x 18 DUAL-PORT
STATIC RAM
IDT70V38L
Features
â True Dual-Ported memory cells which allow simultaneous
access of the same memory location
â High-speed access
â Commercial: 15/20ns (max.)
â Industrial: 20ns (max.)
â Low-power operation
â IDT70V38L
Active: 440mW (typ.)
Standby: 660µW (typ.)
â Dual chip enables allow for depth expansion without
external logic
â IDT70V38 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
â M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
â Busy and Interrupt Flags
â On-chip port arbitration logic
â Full on-chip hardware support of semaphore signaling
between ports
â Fully asynchronous operation from either port
â Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
â LVTTL-compatible, single 3.3V (±0.3V) power supply
â Available in a 100-pin TQFP
â Industrial temperature range (â40°C to +85°C) is available
for selected speeds
â Green parts available, see ordering information
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O 9-17L
I/O 0-8L
BUSYL(1,2)
I/O
Control
I/O
Control
A15L
A0L
Address
Decoder
16
64Kx18
MEMORY
ARRAY
70V38
16
CE0L
CE1L
OEL
R/WL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INT
(2)
L
M/S(1)
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
1
©2015 Integrated Device Technology, Inc.
Address
Decoder
CE0R
CE1R
OER
R/WR
I/O9-17R
I/O0-8R
BUSYR (1,2)
.
A15R
A0R
SEMR
INTR (2)
4850 drw 01
MAY 2015
DSC-4850/5
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