IDT70V3599 Datasheet, PDF (1/23 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

HIGH-SPEED 3.3V
128/64K x 36
SYNCHRONOUS
DUAL-PORT STATIC RAM
IDT70V3599/89S
WITH 3.3V OR 2.5V INTERFACE
Features:
◆ _{True Dual-Port memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed data access}
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
◆ _{Selectable Pipelined or Flow-Through output mode}
◆ _{Counter enable and repeat features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{Full synchronous operation on both ports}
– 6ns cycle time, 166MHz operation (12Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ _{Separate byte controls for multiplexed bus and bus}
matching compatibility
◆ _{Dual Cycle Deselect (DCD) for Pipelined Output mode}
◆ _{LVTTL- compatible, 3.3V (±150mV) power supply}
for core
◆ _{LVTTL compatible, selectable 3.3V (±150mV) or 2.5V}
(±100mV) power supply for I/Os and control signals on
each port
◆ _{Industrial temperature range (-40°C to +85°C) is}
available at 133MHz.
◆ _{Available in a 208-pin Plastic Quad Flatpack (PQFP),}
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
◆ _{Supports JTAG features compliant with IEEE 1149.1}
Functional Block Diagram
BE3L
BE3R
BE2L
BE2R
BE1L
BE1R
BE0L
BE0R
FT/PIPEL
R/WL
CE0L
CE1L
OEL
0a 1a
1/0
a
0b 1b
b
0c 1c
c
0d 1d
d
1
0
1/0
BB BBBB BB
WW WWWW WW
01 2332 10
L L L L RR RR
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
FT/PIPEL
1d 0d 1c 0c 1b 0b 1a 0a
0/1
a b cd
I/O0L - I/O35 L
CLKL
A16L(1)
A0L
REPEATL
ADSL
CNTENL
NOTE:
1. A16 is a NC for IDT70V3589.
©2003 Integrated Device Technology, Inc.
Counter/
Address
Reg.
TDI
TDO
128K x 36
MEMORY
ARRAY
Din_L
Din_R
ADDR_L
ADDR_R
JTAG
1
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
1/0
a
1
0
1 /0
FT/PIPER
R/WR
CE0R
CE1R
OER
0a 1a 0b 1b 0c 1c 0d 1d
0/1
d cba
FT/PIPER
Counter/
Address
Reg.
TCK
TMS
TRST
I/O0R - I/O35R
CLKR
A 16 R^{( 1)}
A0R
REPEATR
ADSR
CNTENR
,
5617 tbl 01
MAY 2003
DSC 5617/6