IDT70V3569S_14 Datasheet, PDF (1/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V 16K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Š _{WITH 3.3V OR 2.5V INTERFACE}
IDT70V3569S
Features:
◆ _{True Dual-Port memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed clock to data access}
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
◆ _{Pipelined output mode}
◆ _{Counter enable and reset features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{Full synchronous operation on both ports}
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ _{Separate byte controls for multiplexed bus and bus}
matching compatibility
◆ _{LVTTL- compatible, single 3.3V (±150mV) power supply for}
core
◆ _{LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)}
power supply for I/Os and control signals on each port
◆ _{Industrial temperature range (-40°C to +85°C) is}
available for selected speeds
◆ _{Available in a 208-pin Plastic Quad Flatpack (PQFP),}
208-ball fine-pitch Ball Grid Array, and 256-pin Ball
Grid Array
◆ _{Green parts availble, see ordering instructions}
Functional Block Diagram
BE3L
BE3R
BE2L
BE1L
BE2R
BE1R
BE0L
BE0R
R/WL
CE0L
CE1L
OEL
I/O0L- I/O35L
CLKL
A13L
A0L
CNTRSTL
ADSL
CNTENL
Counter/
Address
Reg.
©2014 Integrated Device Technology, Inc.
B B B B B BB B
W W W W W WW W
0 1 2 3 3 21 0
L L L L R RR R
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
16K x 36
MEMORY
ARRAY
Din_L
Din_R
ADDR_L
ADDR_R
1
R/WR
CE0R
CE1R
OER
Counter/
Address
Reg.
I/O0R - I/O35R
A13R
, _CLKR
A0R
CNTRSTR
ADSR
CNTENR
4831 tbl 01
OCTOBER 2014
DSC 4831/13