IDT70V3379S_15 Datasheet, PDF (1/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V 32K x 18
SYNCHRONOUS PIPELINED
IDT70V3379S
DUAL-PORT STATIC RAM
Š _{WITH 3.3V OR 2.5V INTERFACE}
Features:
◆ _{True Dual-Port memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed clock to data access}
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
◆ _{Pipelined output mode}
◆ _{Counter enable and reset features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{Full synchronous operation on both ports}
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ _{Separate byte controls for multiplexed bus and bus}
matching compatibility
◆ _{LVTTL- compatible, single 3.3V (±150mV) power supply for}
core
◆ _{LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)}
power supply for I/Os and control signals on each port
◆ _{Industrial temperature range (-40°C to +85°C) is}
available for selected speeds
◆ _{Available in a 128-pin Thin Quad Plastic Flatpack (TQFP)}
and 208-pin fine pitch Ball Grid Array, and 256-pin
Ball Grid Array
◆ _{Green parts available, see ordering information}
Functional Block Diagram
UBL
LBL
R/WL
CE0L
CE1L
OEL
I/O0 L - I/O1 7 L
CLKL
A14L
A0L
CNTRSTL
ADSL
CNTENL
Counter/
Address
Reg.
BB
WW
01
LL
BB
WW
10
RR
Dout0-8_L
Dout0-8_R
Dout9-17_L _{Dout9-17_R}
32K x 18
MEMORY
ARRAY
Din_L
Din_R
ADDR_L
ADDR_R
Counter/
Address
Reg.
UBR
LBR
R/WR
CE0R
CE1R
OER
,.
I/O0R - I/O17R
CLKR
A14R
A0R
CNTRSTR
ADSR
CNTENR
4833 tbl 01
1
©2015 Integrated Device Technology, Inc.
AUGUST 2015
DSC 4833/13