IDT70V19L Datasheet, PDF (1/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 128K x 9 DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V
128K x 9 DUAL-PORT
STATIC RAM
IDT70V19L
Features
◆ _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed access}
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
◆ _{Low-power operation}
– IDT70V19L
Active: 440mW (typ.)
Standby: 660µW (typ.)
◆ _{Dual chip enables allow for depth expansion without}
external logic
◆ _{IDT70V19 easily expands data bus width to 18 bits or}
more using the Master/Slave select when cascading more
than one device
Functional Block Diagram
R/W L
CE0L
CE1L
OE_L
◆ _{M/S = VIH for BUSY output flag on Master,}
M/S = VIL for BUSY input on Slave
◆ _{Busy and Interrupt Flags}
◆ _{On-chip port arbitration logic}
◆ _{Full on-chip hardware support of semaphore signaling}
between ports
◆ _{Fully asynchronous operation from either port}
◆ _{LVTTL-compatible, single 3.3V (±0.3V) power supply}
◆ _{Available in a 100-pin TQFP}
◆ _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
R/WR
CE0R
CE1R
OER
I/O 0-8L
I/O
Control
I/O
Control
BUSY
(1,2)
L
A16L
A0L
Address
Decoder
17
CE _0L
CE1L
OE L
R/W L
128Kx9
MEMORY
ARRAY
70V19
17
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEM L
INT
(2)
L
M/S ⁽¹⁾
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
1
©2003 Integrated Device Technology, Inc.
Address
Decoder
I/O 0-8R
BUSY
(1,2)
R
A16R
A 0R
CE0R
CE1R
OER
R/WR
4853 drw 01
SEMR
INT R⁽²⁾
SEPTEMBER 2003
DSC-4853/4