IDT70V16 Datasheet, PDF (1/18 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V
16/8K X 9 DUAL-PORT
STATIC RAM
PRELIMINARY
IDT70V16/5S/L
.eatures
x _{True Dual-Ported memory cells which allow simultaneous}
reads of the same memory location
x _{High-speed access}
– Commercial:15/20/25ns (max.)
– Industrial: 20ns (max.)
x _{Low-power operation}
– IDT70V16/5S
Active: 430mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V16/5L
Active: 415mW (typ.)
Standby: 660µW (typ.)
x _{IDT70V16/5 easily expands data bus width to 18 bits or}
more using the Master/Slave select when cascading more
than one device
x _{M/S = VIH for BUSY output flag on Master}
M/S = VIL for BUSY input on Slave
x _{Busy and Interrupt Flag}
x _{On-chip port arbitration logic}
x _{Full on-chip hardware support of semaphore signaling}
between ports
x _{Fully asynchronous operation from either port}
x _{LVTTL-compatible, single 3.3V (+0.3V) power supply}
x _{Available in 68-pin PLCC and an 80-pin TQFP}
x _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
.unctional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O8L
BUSYL^(2,3)
A13L⁽¹⁾
A0L
I/O
Control
I/O
Control
Address
Decoder
14
CEL
OEL
R/WL
MEMORY
ARRAY
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL⁽³⁾
M/S
NOTES:
1. A13 is a NC for IDT70V15.
2. In MASTER mode: BUSY is an output and is a push-pull driver
In SLAVE mode: BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
1
©2002 Integrated Device Technology, Inc.
Address
Decoder
CER
OER
R/WR
I/O0R-I/O8R
BUSYR^(2,3)
A13R⁽¹⁾
A0R
SEMR
INTR⁽³⁾
5669 drw 01
AUGUST 2002
DSC 5669/1