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IDT70V07S_05 Datasheet, PDF (1/18 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM | |||
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HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
IDT70V07S/L
Features
â True Dual-Ported memory cells which allow simultaneous
access of the same memory location
â High-speed access
â Commercial: 25/35/55ns (max.)
â Industral: 25ns (max.)
â Low-power operation
â IDT70V07S
Active: 300mW (typ.)
Standby: 3.3mW (typ.)
â IDT70V07L
Active: 300mW (typ.)
Standby: 660µW (typ.)
â Interrupt Flag
â IDT70V07 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
â M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
â On-chip port arbitration logic
â Full on-chip hardware support of semaphore signaling
between ports
â Fully asynchronous operation from either port
â TTL-compatible, single 3.3V (±0.3V) power supply
â Available in 68-pin PGA and PLCC, and a 80-pin TQFP
â Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL(1,2)
A14L
A0L
I/O
Control
I/O
Control
Address
Decoder
15
CEL
OEL
R/WL
MEMORY
ARRAY
15
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL(2)
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
1
©2004 Integrated Device Technology, Inc.
Address
Decoder
I/O0R-I/O7R
,
BUSYR(1,2)
A14R
A0R
CER
OER
R/WR
SEMR
INTR(2)
2943 drw 01
OCTOBER 2004
DSC 2943/6
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