IDT70V07S Datasheet, PDF (1/18 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology, Inc.
HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
IDT70V07S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Commercial: 25/35/55ns (max.)
• Low-power operation
— IDT70V07S
Active: 450mW (typ.)
Standby: 5mW (typ.)
— IDT70V07L
Active: 450mW (typ.)
Standby: 5mW (typ.)
• IDT70V07 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• LVTTL-compatible, single 3.3V (±0.3V) power supply
• Available in 68-pin PGA, 68-pin PLCC, and a 64-pin
TQFP
DESCRIPTION:
The IDT70V07 is a high-speed 32K x 8 Dual-Port Static
RAM. The IDT70V07 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 16-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
FUNCTIONAL BLOCK DIAGRAM
OEL
W^CEL
R/ L
OER
W^CER
R/ R
I/O0L- I/O7L
(1,2)
BUSYL
A14L
A0L
I/O
Control
I/O
Control
Address
Decoder
15
CEL
OEL
W R/ L
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
15
CER
W ^OER
R/ R
SEML
(2)
M/S
INTL
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.37
I/O0R-I/O7R
BUSYR(1,2)
A14R
A0R
SEMR
(2)
INTR
2943 drw 01
OCTOBER 1996
DSC-2943/3
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