IDT70V05S_12 Datasheet, PDF (1/22 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

HIGH-SPEED 3.3V
8K x 8 DUAL-PORT
STATIC RAM
IDT70V05S/L
Features
◆ _{True Dual-Ported memory cells which allow simultaneous}
reads of the same memory location
◆ _{High-speed access}
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20ns (max.)
◆ _{Low-power operation}
– IDT70V05S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V05L
Active: 380mW (typ.)
Standby: 660µW (typ.)
◆ _{IDT70V05 easily expands data bus width to 16 bits or more}
using the Master/Slave select when cascading more than
one device
◆ _{M/S = VIH for BUSY output flag on Master}
M/S = VIL for BUSY input on Slave
◆ _{Interrupt Flag}
◆ _{On-chip port arbitration logic}
◆ _{Full on-chip hardware support of semaphore signaling}
between ports
◆ _{Fully asynchronous operation from either port}
◆ _{TTL-compatible, single 3.3V (±0.3V) power supply}
◆ _{Available in 68-pin PGA and PLCC, and a 64-pin TQFP}
◆ _{Industrial temperature range (-40°C to +85°C) is available}
for selected speeds
◆ _{Green parts available, see ordering information}
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL^(1,2)
A12L
A0L
I/O
Control
I/O
Control
Address
Decoder
13
CEL
OEL
R/WL
MEMORY
ARRAY
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL⁽²⁾
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
Address
Decoder
CER
OER
R/WR
1
©2012 Integrated Device Technology, Inc.
,
I/O0R-I/O7R
BUSYR^(1,2)
A12R
A0R
SEMR
INTR⁽²⁾
2942 drw 01
JUNE 2012
DSC 2941/10