IDT70T9169L Datasheet, PDF (1/16 Pages) Integrated Device Technology – HIGH-SPEED 2.5V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

HIGH-SPEED 2.5V
16/8K X 9 SYNCHRONOUS
PIPELINED
DUAL-PORT STATIC RAM
PRELIMINARY
IDT70T9169/59L
.eatures
x _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
x _{High-speed clock to data access}
– Commercial:7.5/9/12ns (max.)
– Industrial: 9ns (max.)
x _{Low-power operation}
– IDT70T9169/59L
Active: 225mW (typ.)
Standby: 1.5mW (typ.)
x _{Flow-Through or Pipelined output mode on either Port via}
the FT/PIPE pins
x _{Counter enable and reset features}
x _{Dual chip enables allow for depth expansion without}
additional logic
.unctional Block Diagram
x _{Full synchronous operation on both ports}
– 4.0ns setup to clock and 0.5ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
x _{LVTTL- compatible, single 2.5V (±100mV) power supply}
x _{Industrial temperature range (–40°C to +85°C) is}
available for 66MHz
x _{Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-}
pin fine pitch Ball Grid Array (fpBGA) packages.
R/WL
OEL
CE0L
1
CE1L
0
0/1
R/WR
OER
CE0R
1
CE1R
0
0/1
FT/PIPEL
I/O0L - I/O8L
0/1 ¹
0
I/O
Control
I/O
Control
0
1
0/1
A13L⁽¹⁾
A0L
CLKL
ADSL
CNTENL
CNTRSTL
NOTE:
1. A13 is a NC for IDT70T9159.
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
FT/PIPER
I/O0R - I/O8R
A13R⁽¹⁾
A0R
CLKR
ADSR
CNTENR
CNTRSTR
5654 drw 01
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©2002 Integrated Device Technology, Inc.
JULY 2002
DSC-5654/1