IDT70T653M_15 Datasheet, PDF (1/24 Pages) Integrated Device Technology – HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM

HIGH-SPEED 2.5V
512K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
Š _{WITH 3.3V 0R 2.5V INTERFACE}
IDT70T653M
Features
◆ _{True Dual-Port memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed access}
– Commercial: 10/12/15ns (max.)
– Industrial: 12ns (max.)
◆ _{RapidWrite Mode simplifies high-speed consecutive write}
cycles
◆ _{Dual chip enables allow for depth expansion without}
external logic
◆ _{IDT70T653M easily expands data bus width to 72 bits or}
more using the Busy Input when cascading more than one
device
◆ _{Busy input for port contention management}
◆ _{Interrupt Flags}
◆ _{Full on-chip hardware support of semaphore signaling}
between ports
◆ _{Fully asynchronous operation from either port}
◆ _{Separate byte controls for multiplexed bus and bus}
matching compatibility
◆ _{Sleep Mode Inputs on both ports}
◆ _{Single 2.5V (±100mV) power supply for core}
◆ _{LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)}
power supply for I/Os and control signals on each port
◆ _{Includes JTAG functionality}
◆ _{Available in a 256-ball Ball Grid Array}
◆ _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
◆ _{Green parts available, see ordering information}
Functional Block Diagram
BE3L
BE2L
BE1L
BE0L
R/WL
CE0L
CE1L
BB BB BBBB
EE EE EEEE
01 23 3210
L L L L RRRR
BE3R
BE2R
BE1R
BE0R
R/WR
CE0R
CE1R
OEL
I/O0L- I/O35L
Dout0-8_L Dout0-8_R
Dout9-17_L _{Dout9-17_R}
Dout18-26_L Dout18-26_R
Dout27-35_L Dout27-35_R
512K x 36
MEMORY
ARRAY
Di n_L
Di n_R
OER
I/O0R -I/O35R
A18L
Address
A0L
Decoder
ADDR_L ADDR_R
Address
Decoder
A18R
A0R
BUSYL
SEML
INTL(1)
CE0L
CE1L
OEL
R/WL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE0R
TDI
TCK
CE1R
JTAG
TMS
OER
TDO
TRST
R/WR
BUSYR
SEMR
INTR(1)
ZZL(2)
ZZ
CONTROL
ZZR(2)
NOTES:
LOGIC
1. INT is non-tri-state totem-pole outputs (push-pull).
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx and the sleep mode _{5679 drw 01}
pins themselves (ZZx) are not affected during sleep mode.
1
©2015 Integrated Device Technology, Inc.
JUNE 2015
DSC-5679/6