IDT70T633_12 Datasheet, PDF (1/27 Pages) Integrated Device Technology – HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM

HIGH-SPEED 2.5V
IDT70T633/1S
512/256K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
Š _{WITH 3.3V 0R 2.5V INTERFACE}
Features
◆ _{True Dual-Port memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed access}
– Commercial: 10/12/15ns (max.)
– Industrial: 10/12ns (max.)
◆ _{RapidWrite Mode simplifies high-speed consecutive write}
cycles
◆ _{Dual chip enables allow for depth expansion without}
external logic
◆ _{IDT70T633/1 easily expands data bus width to 36 bits or}
more using the Master/Slave select when cascading more
than one device
◆ _{M/S = VIH for BUSY output flag on Master,}
M/S = VIL for BUSY input on Slave
◆ _{Busy and Interrupt Flags}
◆ _{On-chip port arbitration logic}
◆ _{Full hardware support of semaphore signaling between}
ports on-chip
◆ _{Fully asynchronous operation from either port}
◆ _{Separate byte controls for multiplexed bus and bus}
matching compatibility
◆ _{Sleep Mode Inputs on both ports}
◆ _{Supports JTAG features compliant to IEEE 1149.1 in}
BGA-208 and BGA-256 packages
◆ _{Single 2.5V (±100mV) power supply for core}
◆ _{LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)}
power supply for I/Os and control signals on each port
◆ _{Available in a 256-ball Ball Grid Array and 208-ball fine pitch}
Ball Grid Array
◆ _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
◆ _{Green parts available, see ordering information}
Functional Block Diagram
UBL
UBR
LBL
LB R
R/W L
CE0L
CE1L
BB
BB
EE
EE
01
10
LL
RR
R/W R
CE0R
CE1R
OEL
I/O0L- I/O17L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
512/256K x 18
MEMORY
ARRAY
Din_L
Din_R
OER
I/O0R - I/O17R
A18L⁽¹⁾
A0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A18R ⁽¹⁾
A0R
CE0L
CE1L
OEL
R/WL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OER
R/WR
TDI
TDO
C E 0R
CE1R
B U S Y L(2,3)
SEM L
M/S
I NT L(3)
NOTES:
ZZL(4)
ZZ
CONTROL
ZZR ^{(4 )}
1. Address A18x is a NC for IDT70T631.
LOGIC
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3 BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the
sleep mode pins themselves (ZZx) are not affected during sleep mode.
1
©2012 Integrated Device Technology, Inc.
TCK
JT AG
TMS
T R ST
B U S Y R(2,3)
SEM R
IN T R(3)
5670 drw 01
JUNE 2012
DSC-5670/9