IDT70T3719 Datasheet, PDF (1/25 Pages) Integrated Device Technology – HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

HIGH-SPEED 2.5V
256/128K x 72
SYNCHRONOUS
ADVANCED
IDT70T3719/99M
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆ _{True Dual-Port memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed data access}
– Commercial: 3.6ns (166MHz)/
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
◆ _{Separate byte controls for multiplexed bus and bus}
4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz) (max.)
◆ _{Selectable Pipelined or Flow-Through output mode}
◆ _{Counter enable and repeat features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{Interrupt and Collision Detection Flags}
◆ _{Full synchronous operation on both ports}
matching compatibility
◆ _{Dual Cycle Deselect (DCD) for Pipelined Output Mode}
◆ _{2.5V (±100mV) power supply for core}
◆ _{LVTTL compatible, selectable 3.3V (±150mV) or 2.5V}
(±100mV) power supply for I/Os and control signals on
each port
◆ _{Industrial temperature range (-40°C to +85°C) is}
available at 133MHz
– 6ns cycle time, 166MHz operation (23.9Gbps bandwidth)
– Fast 3.6ns clock to data out
– Self-timed write allows fast cycle time
◆ _{Available in a 324-pin Green Ball Grid Array (BGA)}
◆ _{Includes JTAG Functionality}
Functional Block Diagram
BE7L
BE7R
BE0L
BE0R
FT/PIP EL
0a 1a
1/0
a
0h 1h
h
1h 0h
h
1a 0a
1/0
a
FT/PIPER
R/WL
R/WR
CE0L
CE1L
OEL
FT/PIPEL
1
0
1/0
1h 0h
0/1
a
1a 0a
h
Byte 0
I/O0L - I/O71L
CLKL
A17L(1)
A 0L
REPEATL
ADSL
CN TENL
Byte 7
Counter/
Address
Reg.
B
B
B
B
W
WW
W
0
7
7
0
L
L
R
R
D OUT0-8_ L
D OUT9-17 _L
DO UT18-26_L
D OUT 27-3 5_ L
D OUT 36-4 4_L
D OUT 45-5 3_L
D OUT 54-6 2_L
D OUT 63-7 2_L
D OUT0-8_ R
D OUT9-17 _R
D OU T1 8-2 6_ R
DOUT27 -35_ R
DOUT36 -4 4_ R
DOUT45 -5 3_ R
DOUT54 -6 2_ R
DOUT63 -7 2_ R
256/128K x 72
MEM ORY
ARRAY
DIN_L
DIN_R
ADDR_L
ADDR_R
0a 1a
h
0h 1h
0/1
a
Byte 7
Counter/
Address
Reg.
Byte 0
I/O0R - I/O71R
A17R(1)
CLKR
A 0R
REPE ATR
AD SR
CNTENR
COL L
INTL
CE0L
CE1L
R/WL
INTERRUPT
COLLISION
DETECTION
LOGIC
CE0R
CE1R
R/WR
TDI
T DO
COL R
INTR
NOTES:
ZZ
(2)
L
ZZ
CONTROL
LOGIC
ZZ
(2)
R
1. Address A17 is a NC for the IDT70T3799.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
1
©2005 Integrated Device Technology, Inc.
C E0 R
1
C E1 R
0
1/0
OER
,
FT/PIPER
,
JTAG
TC K
TMS
TRST
5687 drw 01
JUNE 2005
DSC 5687/1