IDT70T3519 Datasheet, PDF (1/28 Pages) Integrated Device Technology – HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

HIGH-SPEED 2.5V
256/128/64K x 36
SYNCHRONOUS
IDT70T3519/99/89S
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆ _{True Dual-Port memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed data access}
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
◆ _{Selectable Pipelined or Flow-Through output mode}
◆ _{Counter enable and repeat features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{Interrupt and Collision Detection Flags}
◆ _{Full synchronous operation on both ports}
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ _{Separate byte controls for multiplexed bus and bus}
matching compatibility
◆ _{Dual Cycle Deselect (DCD) for Pipelined Output Mode}
◆ _{2.5V (±100mV) power supply for core}
◆ _{LVTTL compatible, selectable 3.3V (±150mV) or 2.5V}
(±100mV) power supply for I/Os and control signals on
each port
◆ _{Industrial temperature range (-40°C to +85°C) is}
available at 166MHz and 133MHz
◆ _{Available in a 256-pin Ball Grid Array (BGA), a 208-pin}
Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball
Grid Array (fpBGA)
◆ _{Supports JTAG features compliant with IEEE 1149.1}
◆ _{Due to limited pin count JTAG is not supported on the 208-}
pin PQFP package
Functional Block Diagram
BE3L
BE3R
BE2L
BE2R
B E1 L
BE1R
BE0L
BE0R
FT/PIP EL
0a 1a
1/0
a
0b 1b 0c 1c
b
c
0d 1d
d
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
1/0
a
FT/PIPER
R/WL
R/WR
CE0L
1
CE1L
0
1/0
OEL
BB BBBB BB
WW WWWW WW
01 2332 10
L L L L RR RR
Do ut0 -8 _L
Do ut9 -1 7_ L
Do ut1 8-26 _L
Do ut2 7-35 _L
D o ut0 -8 _R
D ou t9-17 _R
D out18-26_R
D out27-35_R
C E0 R
1
C E1 R
0
1/0
OER
FT/PIPEL
1d 0d 1c 0c 1b 0b 1a 0a
0/1
a bc d
256/128/64K x 36
MEM ORY
ARRAY
0a 1a 0b 1b 0c 1c 0d 1d
0/1
dc b a
,
FT/PIPER
I/O0L - I/O35L
Din_L
Din_R
I/O0R - I/O35R
CLKL
A17L⁽¹⁾
A0L
REPEATL
ADSL
CN TENL
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
CLKR
A17R(1)
A0R
REPE ATR
AD SR
CNTENR
COL L
INTL
CE 0 L
CE1L
R /WL
INTERRUPT
COLLISION
DETECTION
LOGIC
CE0 R
C E1 R
R/WR
TDI
TDO
COLR
INTR
NOTES:
ZZL(2)
ZZ
CONTROL
LOGIC
ZZ R(2)
1. Address A17 is a NC for the IDT70T3599. Also, Addresses A17 and A16 are NC's for the IDT70T3589.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
1
©2004 Integrated Device Technology, Inc.
,
TCK
JTAG
TMS
TRST
5666 drw 01
APRIL 2004
DSC 5666/6