IDT70T3399 Datasheet, PDF (1/28 Pages) Integrated Device Technology – HIGH-SPEED 2.5V 512/256/128K X 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

HIGH-SPEED 2.5V
512/256/128K X 18
SYNCHRONOUS
PRELIMINARY
IDT70T3339/19/99S
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
– Data input, address, byte enable and control registers
◆ _{True Dual-Port memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed data access}
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
◆ _{Selectable Pipelined or Flow-Through output mode}
◆ _{Counter enable and repeat features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{Interrupt and Collision Detection Flags}
◆ _{Full synchronous operation on both ports}
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Self-timed write allows fast cycle time
◆ _{Separate byte controls for multiplexed bus and bus}
matching compatibility
◆ _{Dual Cycle Deselect (DCD) for Pipelined Output Mode}
◆ _{2.5V (±100mV) power supply for core}
◆ _{LVTTL compatible, selectable 3.3V (±150mV) or 2.5V}
(±100mV) power supply for I/Os and control signals on
each port
◆ _{Industrial temperature range (-40°C to +85°C) is}
available at 166MHz and 133MHz
◆ _{Available in a 256-pin Ball Grid Array (BGA), a 144-pin Thin}
Quad Flatpack (TQFP) and 208-pin fine pitch Ball Grid Array
(fpBGA)
◆ _{Supports JTAG features compliant with IEEE 1149.1}
◆ _{Due to limited pin count JTAG, Collision Detection and}
Interrupt are not supported on the 144-pin TQFP package
Functional Block Diagram
UBL
UBR
LBL
LBR
FT/PIPEL
R/WL
CE0L
CE1L
OEL
0a 1a 0b 1b
1/0
a
b
1
0
1/0
BB
WW
01
LL
Dout0-8_L
Dout9-17_L
BB
WW
10
RR
Dout0-8_R
Dout9-17_R
1b 0b 1a 0a
1/0
b
a
1
0
1/0
FT/PIPER
R/WR
CE0R
CE1R
OER
FT/PIPEL
1b 0b 1a 0a
0/1
ab
512/256/128K x 18
MEMORY
ARRAY
0a 1a 0b
1b
0/1
ba
,
FT/PIPER
I/O0L - I/O17L
CLKL
A 18L^{(1 )}
A0L
REPEATL
ADSL
CNTENL
Counter/
Address
Reg.
Din_L
Din_R
ADDR_L
ADDR_R
I/O0R - I/O17R
Counter/
Address
Reg.
,
CLKR
A 18R^{( 1)}
A0R
REPEATR
ADSR
CNTENR
CE 0 L
CE1L
R/W L
INTE RRUPT
CO LLISION
DETE CTION
LOGIC
CE0 R
CE1R
R /W R
COL L
INTL
COLR
INTR
ZZ
(2)
L
ZZ
CO NTROL
LO GIC
ZZR(2)
NOTES:
1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
TDI
TCK
JTAG
TMS
TDO
TRST
5652 drw 01
NOVEMBER 2003
1
©2003 Integrated Device Technology, Inc.
DSC-5652/3