IDT70T16 Datasheet, PDF (1/18 Pages) Integrated Device Technology – HIGH-SPEED 2.5V 16/8K X 9 DUAL-PORT STATIC RAM

HIGH-SPEED 2.5V
16/8K X 9 DUAL-PORT
STATIC RAM
PRELIMINARY
IDT70T16/5L
.eatures
x _{True Dual-Ported memory cells which allow simultaneous}
reads of the same memory location
x _{High-speed access}
– Commercial:20/25ns (max.)
– Industrial: 25ns (max.)
x _{Low-power operation}
– IDT70T16/5L
Active: 200mW (typ.)
Standby: 600µW (typ.)
x _{IDT70T16/5 easily expands data bus width to 18 bits or}
more using the Master/Slave select when cascading more
than one device
x _{M/S = VIH for BUSY output flag on Master}
M/S = VIL for BUSY input on Slave
x _{Busy and Interrupt Flag}
x _{On-chip port arbitration logic}
x _{Full on-chip hardware support of semaphore signaling}
between ports
x _{Fully asynchronous operation from either port}
x _{LVTTL-compatible, single 2.5V (±100mV) power supply}
x _{Available in an 80-pin TQFP and 100-pin fpBGA}
x _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
.unctional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O8L
BUSYL^(2,3)
A13L⁽¹⁾
A0L
I/O
Control
I/O
Control
Address
Decoder
14
CEL
OEL
R/WL
MEMORY
ARRAY
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL⁽³⁾
M/S
NOTES:
1. A13 is a NC for IDT70T15.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
Address
Decoder
CER
OER
R/WR
I/O0R-I/O8R
BUSYR^(2,3)
A13R⁽¹⁾
A0R
SEMR
INTR⁽³⁾
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©2002 Integrated Device Technology, Inc.
AUGUST 2002
DSC 5663/1