IDT70P3537 Datasheet, PDF (1/20 Pages) Integrated Device Technology – 512K/256K x36 SYNCHRONOUS DUAL QDR-II

512K/256K x36
SYNCHRONOUS
DUAL QDR-II^TM
®
PRELIMINARY DATASHET
IDT70P3537
IDT70P3517
Features
◆ _{18Mb Density (512K x 36)}
– Also available 9Mb Density (256K x 36)
◆ _{QDR-II x 36 Burst-of-2 Interface}
– Commercial: 233MHz, 250MHz
◆ _{Two independent ports}
– True Dual-Port Access to common memory
◆ _{Separate, Independent Read and Write Data Buses on each}
Port
– Supports concurrent transactions
◆ _{Two-Word Burst on all DPRAM accesses}
◆ _{DDR (Double Data Rate) Multiplexed Address Bus}
– One Read and One Write request per clock cycle
◆ _{DDR (Double Data Rate) Data Buses}
– Four word burst data (Two Read and Two Write) per clock on
each port
– Four word transfers each of Read & Write per clock cycle per
port (four word bursts on 2 ports)
◆ _{Octal Data Rate}
◆ _{Port Enable pins (E0,E1) for depth expansion}
◆ _{Dual Echo Clock Output with DLL-based phase alignment}
◆ _{High Speed Transceiver Logic inputs}
– scaled to receive signals from 1.4V to 1.9V
◆ _{Scalable output drivers}
– Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V
– Output impedance adjustable from 35 ohms to 70 ohms
◆ _{1.8V Core Voltage (VDD)}
◆ _{576-ball Flip Chip BGA (25mm x 25mm, 1.0mm ball pitch)}
◆ _{JTAG Interface - IEEE 1149.1 Compliant}
Functional Block Diagram
EL[1:0]
D0 L - D3 5 L
KL
KL
A0L- A17L⁽²⁾
RL
WL
BW0 L - BW3 L
KL
KL
VREFL
LEFT PORT
DATA
REGISTER
AND LOGIC
ZQL ⁽¹⁾
Q0 L - Q3 5 L
CQL, CQL
LEFT PORT
ADDRESS
REGISTER
AND LOGIC
VREFL
KL
KL
CL
CL, CL
OR _{KL, KL}
TDI
TDO
EP[1:0]
WRITE DRIVER
512/256K x 36
MEMORY
ARRAY
ADDRESS DECODE
JTAG
TCK
TMS
TRST
VREFR
KR
KR
CR
CR, CR
OR _{KR, KR}
RIGHT PORT
DATA
REGISTER
AND LOGIC
ZQR ⁽¹⁾
Q0 R - Q3 5 R
CQR, CQR
RIGHT PORT
ADDRESS
REGISTER
AND LOGIC
ER[1:0]
D0 R - D3 5 R
KR
KR
A0R- A17R⁽²⁾
RR
WR
BW0 R - BW3 R
KR
KR
VREFR
5677 drw01
NOTES:
1. Input pin to adjust the device outputs to the system data bus impedance.
2. Address A17 is a INC for IDT70P3517. Disabled input pin (Diode tied to VDD and VSS).
July 16, 2007
©2007 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice. NOT AN OFFER FOR SALE The information
presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale
or an offer for sale that creates a contractual power of acceptance. "QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semicondor, IDT, and Micron Tecnology, Inc."
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