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IDT709379 Datasheet, PDF (1/16 Pages) Integrated Device Technology – HIGH-SPEED SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM | |||
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HIGH-SPEED 32/16K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT709379/69L
Features
â True Dual-Ported memory cells which allow simultaneous
access of the same memory location
â High-speed clock to data access
â Commercial: 7.5/9/12ns (max.)
â Insustrial: 9ns (max.)
â Low-power operation
â IDT709379/69L
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
â Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
â Counter enable and reset features
â Dual chip enables allow for depth expansion without
additional logic
â Full synchronous operation on both ports
â 4ns setup to clock and 0ns hold on all control, data, and
address inputs
â Data input, address, and control registers
â Fast 7.5ns clock to data out in the Pipelined output mode
â Self-timed write allows fast cycle time
â 10ns cycle time, 100MHz operation in Pipelined output mode
â Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
â TTL- compatible, single 5V (±10%) power supply
â Industrial temperature range (â40°C to +85°C) is
available for selected speeds
â Available in a 100-pin Thin Quad Flatpack (TQFP) package
â Green parts available, see ordering information
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
1
0
0/1
LBL
OEL
FT/PIPEL
I/O9L-I/O17L
I/O0L-I/O8L
A14L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1
1b 0b
b
a 1a 0a
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
1
0
0/1
0a 1a a b0b 1b 0/1
Counter/
Address
Reg.
NOTE:
1. A14X is a NC for IDT709369.
1
©2015 Integrated Device Technology, Inc.
R/WR
UBR
CE0R
CE1R
LBR
OER
FT/PIPER
I/O9R-I/O17R
I/O0R-I/O8R
A14R(1)
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4845 drw 01
JULY 2015
DSC-4845/7
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