IDT709169L Datasheet, PDF (1/16 Pages) Integrated Device Technology – HIGH-SPEED 16/8K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

HIGH-SPEED 16/8K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT709169/59L
Features
◆ _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed clock to data access}
– Commercial: 6.5/7.5/9ns (max.)
Industrial: 7.5ns (max.)
◆ _{Low-power operation}
– IDT709169/59L
Active: 925mW (typ.)
Standby: 2.5mW (typ.)
◆ _{Flow-Through or Pipelined output mode on either Port via}
the FT/PIPE pins
◆ _{Counter enable and reset features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
Functional Block Diagram
◆ _{Full synchronous operation on both ports}
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time,100MHz operation in Pipelined output mode
◆ _{TTL- compatible, single 5V (±10%) power supply}
◆ _{Industrial temperature range (–40°C to +85°C) is}
available for 83MHz
◆ _{Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-}
pin fine pitch Ball Grid Array (fpBGA) packages.
R/WL
OEL
CE0L
1
CE1L
0
0/1
R/WR
OER
CE0R
1
CE1R
0
0/1
FT/PIPEL
I/O0L - I/O8L
0/1 ¹
0
I/O
Control
I/O
Control
0
1
0/1
A13L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
NOTE:
1. A13 is a NC for IDT709159.
FT/PIPER
I/O0R - I/O8R
A13R(1)
A0R
CLKR
ADSR
CNTENR
CNTRSTR
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©2009 Integrated Device Technology, Inc.
JANUARY 2009
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