IDT709149S Datasheet, PDF (1/10 Pages) Integrated Device Technology – HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM

HIGH-SPEED 36K (4K x 9-BIT)
SYNCHRONOUS PIPELINED
DUAL-PORT SRAM
IDT709149S
Features
x _{Architecture based on Dual-Port SRAM cells}
– Allows full simultaneous access from both ports
x _{High-speed clock-to-data output times}
– Commercial: 8/10/12ns (max.)
x _{Low-power operation}
– IDT709149S
Active: 1500mW (typ.)
Standby: 75mW (typ.)
x _{4K X 9 bits}
x _{Synchronous operation}
– 4ns setup to clock, 1ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 8ns clock to data out
x _{13ns cycle time, 76MHz operation in pipeline mode}
– Self-timed write allows for fast cycle times
x _{TTL-compatible, singles 5V (±10%) power supply}
x _{Clock Enable feature}
x _{Guaranteed data output hold times}
x _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds.
Description
The IDT709149 is a high-speed 4K x 9 bit synchronous Dual-Port
SRAM. The memory array is based on Dual-Port memory cells to allow
simultaneous access from both ports. Registers on control, data, and
address inputs provide low set-up and hold times. The timing latitude
provided by this approach will allow systems to be designed with very
Functional Block Diagram
I/O0-8L
OEL
CLKL
CLKENL
R/WL
CEL
REG
WRITE
LOGIC
MMYAAREERRMMRAOOAYRRYY
WRITE
LOGIC
SENSE
SENSE
AMPS _{DECODER DECODER} AMPS
I/O0-8R
FT/PIPEDR
0/1
0
1
REG
en
REG
en
Self-
timed
Write
Logic
A0L-A11L A0R-A11R
Self-
timed
Write
Logic
OER
CLKR
CLKENR
REG
R/WR
CER
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©1999 Integrated Device Technology, Inc.
SEPTEMBER 1999
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