IDT709089S Datasheet, PDF (1/17 Pages) Integrated Device Technology – HIGH-SPEED 64K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM

HIGH-SPEED 64K x 8
SYNCHRONOUS
DUAL-PORT STATIC RAM
PRELIMINARY
IDT709089S/L
Features:
x _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
x _{High-speed clock to data access}
– Commercial: 9/12/15ns (max.)
x _{Low-power operation}
– IDT709089S
Active: 950mW (typ.)
Standby: 5mW (typ.)
– IDT709089L
Active: 950mW (typ.)
Standby: 1mW (typ.)
x _{Flow-Through or Pipelined output mode on either port via}
the FT/PIPE pin
x _{Counter enable and reset features}
x _{Dual chip enables allow for depth expansion without}
additional logic
x _{Full synchronous operation on both ports}
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66MHz operation in the Pipelined
output mode
x _{TTL- compatible, single 5V (±10%) power supply}
x _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
x _{Available in 100-pin Thin Quad Flatpack (TQFP) package}
Functional Block Diagram
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1
CE1R
0
0/1
FT/PIPEL
I/O0L - I/O7L
A15L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1 ¹
0
I/O
Control
I/O
Control
0
1
0/1
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
FT/PIPER
I/O0R - I/O7R
A15R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
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©2000 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-3242/10