IDT707288S Datasheet, PDF (1/16 Pages) Integrated Device Technology – HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS

HIGH-SPEED
64K x 16 BANK-SWITCHABLE
DUAL-PORTED SRAM WITH
EXTERNAL BANK SELECTS
IDT707288S/L
Features
x _{64K x 16 Bank-Switchable Dual-Ported SRAM Architecture}
– Four independent 16K x 16 banks
– 1 Megabit of memory on chip
x _{Fast asynchronous address-to-data access time: 15ns}
x _{User-controlled input pins included for bank selects}
x _{Independent port controls with asynchronous address &}
data busses
x _{Four 16-bit mailboxes available to each port for inter-}
processor communications; interrupt option
x _{Interrupt flags with programmable masking}
x _{Dual Chip Enables allow for depth expansion without}
external logic
x _{UB and LB are available for x8 or x16 bus matching}
x _{TTL-compatible, single 5V (±10%) power supply}
x _{Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)}
Functional Block Diagram
R/WL
CE0L
CE1L
UBL
LBL
OEL
CONTROL
LOGIC
I/O8L-15L
I/O0L-7L
I/O
CONTROL
A13L
A0L(1)
ADDRESS
DECODE
MUX
16Kx16
MEMORY
ARRAY
(BANK 0)
MUX
MUX
16Kx16
MEMORY
ARRAY
(BANK 1)
MUX
CONTROL
LOGIC
I/O
CONTROL
R/WR
CE0R
CE1R
UBR
LBR
OER
I/O8R-15R
I/O0R-7R
ADDRESS
DECODE
A13R
A0R(1)
BA1L
BA0L
BANK
DECODE
MUX
BANK
DECODE
BA1R
BA0R
16Kx16
MEMORY
ARRAY
(BANK 3)
MUX
BKSEL3(2)
BKSEL0(2)
BANK
SELECT
MBSELL
INTL
A5L(1)
A0L(1)
LBL/UBL
OEL
R/WL
CEL
MAILBOX
INTERRUPT
LOGIC
A5R(1)
A0R(1)
LBR/UBR
OER
R/WR
CER
MBSELR
INTR
3592 drw 01
NOTES:
1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins
serve as mailbox address inputs.
2 . Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for
more details.
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©2000 Integrated Device Technology, Inc.
MAY 2000
DSC 3592/7