IDT707278_07 Datasheet, PDF (1/16 Pages) Integrated Device Technology – HIGH-SPEED 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS

HIGH-SPEED
32K x 16 BANK-SWITCHABLE
DUAL-PORTED SRAM WITH
EXTERNAL BANK SELECTS
IDT707278S/L
Features
◆ _{32K x 16 Bank-Switchable Dual-Ported SRAM Architecture} ◆ _{Interrupt flags with programmable masking}
– Four independent 8K x 16 banks
◆ _{Dual Chip Enables allow for depth expansion without}
– 512 Kilobit of memory on chip
external logic
◆ _{Fast asynchronous address-to-data access time: 15ns}
◆ _{User-controlled input pins included for bank selects}
◆ _{Independent port controls with asynchronous address &}
R _{data busses}
◆ _{Four 16-bit mailboxes available to each port for inter-}
O _{processor communications; interrupt option}
◆ _{UB and LB are available for x8 or x16 bus matching}
◆ _{TTL-compatible, single 5V (±10%) power supply}
◆ _{Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)}
F _{Functional Block Diagram}
ED _R/WL
CE0L
D _CE1L
N ^{S UBL}
LBL
OEL
CONTROL
LOGIC
ME _IGN I/O8L-15L
I/O0L-7L
I/O
CONTROL
OM ^ES _A12L
C ^D _A0L(1)
ADDRESS
DECODE
MUX
8Kx16
MEMORY
ARRAY
(BANK 0)
MUX
MUX
8Kx16
MEMORY
ARRAY
(BANK 1)
MUX
CONTROL
LOGIC
I/O
CONTROL
R/WR
CE0R
CE1R
UBR
LBR
OER
I/O8R-15R
I/O0R-7R
ADDRESS
DECODE
A12R
A0R(1)
RE ^{W BA1L}
NOT ^{NE BA0L}
BANK
DECODE
MUX
8Kx16
MEMORY
ARRAY
(BANK 3)
BANK
DECODE
BA1R
BA0R
MUX
BKSEL3(2)
BKSEL0(2)
BANK
SELECT
MBSELL
INTL
A5L(1)
A0L(1)
LBL/UBL
OEL
R/WL
CEL
MAILBOX
INTERRUPT
LOGIC
A5R(1)
A0R(1)
LBR/UBR
OER
R/WR
CER
MBSELR
INTR
,
3739 drw 01
NOTES:
1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins
serve as mailbox address inputs.
2 . Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for
more details.
MAY 2000
1
©2000 Integrated Device Technology, Inc.
DSC 3739/6