|
IDT7027S_15 Datasheet, PDF (1/20 Pages) Integrated Device Technology – HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM | |||
|
HIGH-SPEED
32K x 16 DUAL-PORT
STATIC RAM
IDT7027S/L
Features
â True Dual-Ported memory cells which allow simultaneous
access of the same memory location
â High-speed access
â Commercial: 15/20/25/35/55ns (max.)
â Industrial: 20/25ns (max.)
â Low-power operation
â IDT7027S
Active: 750mW (typ.)
Standby: 5mW (typ.)
â IDT7027L
Active: 750mW (typ.)
Standby: 1mW (typ.)
â Separate upper-byte and lower-byte control for bus
matching capability.
â Dual chip enables allow for depth expansion without
external logic
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
â IDT7027 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
â M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
â Busy and Interrupt Flags
â On-chip port arbitration logic
â Full on-chip hardware support of semaphore signaling
between ports
â Fully asynchronous operation from either port
â TTL-compatible, single 5V (±10%) power supply
â Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin
Ceramic Pin Grid Array (PGA)
â Industrial temperature range (â40°C to +85°C) is available
for selected speeds
â Green parts available, see ordering information
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O 8-15L
I/O 0-7L
BUSYL
I/O
Control
I/O
Control
A14L
A0L
Address
Decoder
A14L
A0L
CE0L
CE1L
OEL
R/WL
32Kx16
MEMORY
ARRAY
7027
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
NOTES:
INT
(2)
L
M/S(2)
1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
1
©2015 Integrated Device Technology, Inc.
Address
Decoder
A14R
A0R
CE0R
CE1R
OER
R/WR
I/O8-15R
I/O0-7R
BUSYR(1,2) .
A14R
A0R
SEMR
INTR(2)
3199 drw 01
AUGUST 2015
DSC 3199/10
|
▷ |