IDT7027S Datasheet, PDF (1/19 Pages) Integrated Device Technology – HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM

HIGH-SPEED
32K x 16 DUAL-PORT
STATIC RAM
IDT7027S/L
Features
x _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
x _{High-speed access}
– Military: 25/35/55ns (max)
– Industrial: 25ns (max.)
– Commercial: 20/25/35/55ns (max.)
x _{Low-power operation}
– IDT7027S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7027L
Active: 750mW (typ.)
Standby: 1mW (typ.)
x _{Separate upper-byte and lower-byte control for bus}
matching capability.
x _{Dual chip enables allow for depth expansion without}
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
external logic
x _{IDT7027 easily expands data bus width to 32 bits or more}
using the Master/Slave select when cascading more than
one device
x _{M/S = VIH for BUSY output flag on Master,}
M/S = VIL for BUSY input on Slave
x _{Busy and Interrupt Flags}
x _{On-chip port arbitration logic}
x _{Full on-chip hardware support of semaphore signaling}
between ports
x _{Fully asynchronous operation from either port}
x _{TTL-compatible, single 5V (±10%) power supply}
x _{Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin}
Ceramic Pin Grid Array (PGA)
x _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O ^8-15L
I/O 0-7L
BUSY
(1,2)
L
I/O
Control
I/O
Control
A14L
A0L
Address
Decoder
A14L
A0L
CE0L
CE1L
OEL
R/WL
32Kx16
MEMORY
ARRAY
7027
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INT
(2)
L
M/S⁽²⁾
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
1
©2000 Integrated Device Technology, Inc.
Address
Decoder
A14R
A0R
CE0R
CE1R
OER
R/WR
I/O8-15R
I/O0-7R
BUSYR^(1,2) _.
A14R
A0R
SEMR
INTR ⁽²⁾
3199 drw 01
MAY 2000
DSC 3199/7