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IDT70261S_15 Datasheet, PDF (1/20 Pages) Integrated Device Technology – HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT | |||
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HIGH-SPEED
IDT70261S/L
16K x 16 DUAL-PORT
STATIC RAM WITH INTERRUPT
Features
â True Dual-Ported memory cells which allow simultaneous
access of the same memory location
â High-speed access
â Commercial: 15/20/25/35/55ns (max.)
â Industrial 20/25ns (max.)
â Low-power operation
â IDT70261S
Active: 750mW (typ.)
Standby: 5mW (typ.)
â IDT70261L
Active: 750mW (typ.)
Standby: 1mW (typ.)
â Separate upper-byte and lower-byte control for multiplexed
bus compatibility
â IDT70261 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
â M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
â Busy and Interrupt Flags
â On-chip port arbitration logic
â Full on-chip hardware support of semaphore signaling
between ports
â Fully asynchronous operation from either port
â TTL-compatible, single 5V (±10%) power supply
â Available in 100-pin Thin Quad Flatpack
â Industrial temperature range (-40OC to +85OC) is available
for selected speeds
â Green parts available. See ordering information
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL
CEL
OEL
LBR
CER
OER
I/O8L-I/O15L
I/O0L-I/O7L
BUSYL(1,2)
I/O
Control
I/O
Control
A13L
A0L
Address
Decoder
14
CEL
OEL
R/WL
MEMORY
ARRAY
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL (2)
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
Address
Decoder
CER
OER
R/WR
1
©2015 Integrated Device Technology, Inc.
I/O8R-I/O15R
I/O0R-I/O7R
BUSYR(1,2)
A13R
A0R
SEMR
INTR(2)
3039 drw 01
JUNE 2015
DSC 3039/11
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