IDT7025S_12 Datasheet, PDF (1/22 Pages) Integrated Device Technology – HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
IDT7024S/L
Features
◆ _{True Dual-Ported memory cells which allow simultaneous}
reads of the same memory location
◆ _{High-speed access}
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
◆ _{Low-power operation}
– IDT7024S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7024L
Active: 750mW (typ.)
Standby: 1mW (typ.)
◆ _{Separate upper-byte and lower-byte control for multiplexed}
bus compatibility
◆ _{IDT7024 easily expands data bus width to 32 bits or more}
using the Master/Slave select when cascading more than
one device
◆ _{M/S = H for BUSY output flag on Master}
M/S = L for BUSY input on Slave
◆ _{Interrupt Flag}
◆ _{On-chip port arbitration logic}
◆ _{Full on-chip hardware support of semaphore signaling}
between ports
◆ _{Fully asynchronous operation from either port}
◆ _{Battery backup operation—2V data retention}
◆ _{TTL-compatible, single 5V (±10%) power supply}
◆ _{Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin}
Quad Flatpack
◆ _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
◆ _{Green parts availble, see ordering information}
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL
CEL
OEL
I/O8L-I/O15L
I/O0L-I/O7L
BUSYL^(1,2)
I/O
Control
I/O
Control
A11L
A0L
Address
Decoder
12
CEL
OEL
R/WL
MEMORY
ARRAY
12
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL⁽²⁾
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
Address
Decoder
CER
OER
R/WR
1
©2013 Integrated Device Technology, Inc.
LBR
CER
OER
I/O8R-I/O15R
I/O0R-I/O7R
BUSYR^(1,2)
A11R
A0R
SEMR
INTR⁽²⁾
2740 drw 01
JUNE 2013
DSC 2740/14