IDT7019L Datasheet, PDF (1/17 Pages) Integrated Device Technology – HIGH-SPEED 128K x 9 DUAL-PORT STATIC RAM

HIGH-SPEED
128K x 9 DUAL-PORT
STATIC RAM
IDT7019L
Features
◆ _{True Dual-Ported memory cells which allow simultaneous}
reads of the same memory location
◆ _{High-speed access}
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
◆ _{Low-power operation}
– IDT7019L
Active: 1W (typ.)
Standby: 1mW (typ.)
◆ _{Dual chip enables allow for depth expansion without}
external logic
◆ _{IDT7019 easily expands data bus width to 18 bits or}
more using the Master/Slave select when cascading more
than one device
◆ _{M/S = VIH for BUSY output flag on Master,}
M/S = VIL for BUSY input on Slave
◆ _{Interrupt Flag}
◆ _{On-chip port arbitration logic}
◆ _{Full on-chip hardware support of semaphore signaling}
between ports
◆ _{Fully asynchronous operation from either port}
◆ _{TTL-compatible, single 5V (±10%) power supply}
◆ _{Available in a 100-pin TQFP}
◆ _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
◆ _{Green parts available, see ordering information}
Functional Block Diagram
R/WL
CE0L
CE1L
OEL
R/WR
CE0R
CE1R
OE R
I/O0-8L
I/O
Control
I/O
Control
BUSYL^(1,2)
A16L
A0L
Address
Decoder
17
CE0L
CE1L
OEL
R/W L
128Kx9
MEMORY
ARRAY
7019
17
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL⁽²⁾
M/S⁽¹⁾
NOTES:
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
1
©2013 Integrated Device Technology, Inc.
Address
Decoder
I/O0-8R
BUSYR^(1,2)
A16R
A0R
CE0R
CE1R
OER
R/WR
SEMR
INT
(2)
R
4840 drw 01
SEPTEMBER 2013
DSC-4840/5