IDT70121S_14 Datasheet, PDF (1/16 Pages) Integrated Device Technology – HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT

Features
✵ _{High-speed access}
– Commercial: 25/35/55ns (max.)
– Industrial: 35ns (max.)
◆ _{Low-power operation}
– IDT70121/70125S
Active: 675mW (typ.)
Standby: 5mW (typ.)
– IDT70121/70125L
Active: 675mW (typ.)
Standby: 1mW (typ.)
HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM
WITH BUSY & INTERRUPT
IDT70121S/L
IDT70125S/L
◆ _{Fully asychronous operation from either port}
◆ _{MASTER IDT70121 easily expands data bus width to 18 bits or}
more using SLAVE IDT70125 chip
◆ _{On-chip port arbitration logic (IDT70121 only)}
◆ _{BUSY output flag on Master; BUSY input on Slave}
◆ _{INT flag for port-to-port communication}
◆ _{Battery backup operation—2V data retention}
◆ _{TTL-compatible, signal 5V (±10%) power supply}
◆ _{Available in 52-pin PLCC}
◆ _{Industrial temperature range (–40°C to +85°C) is available for}
selected speeds
◆ _{Green parts available, see ordering information}
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O8L
BUSYL^(1,2)
A10L
A0L
I/O
Control
I/O
Control
Address
Decoder
11
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
INTERRUPT
LOGIC
Address
Decoder
11
CER
OER
R/WR
I/O0R-I/O8R
BUSYR^(1,2)
A10R
A0R
INTL⁽²⁾
NOTES:
1. 70121 (MASTER): BUSY is non-tri-stated push-pull output.
70125 (SLAVE): BUSY is input.
2. INT is non-tri-stated push-pull output.
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©2014 Integrated Device Technology, Inc.
INTR⁽²⁾
2654 drw 01
AUGUST 2014
DSC 2654/13