IDT7007S Datasheet, PDF (1/21 Pages) Integrated Device Technology – HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM

HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM
IDT7007S/L
Features
x _{True Dual-Ported memory cells which allow simultaneous}
reads of the same memory location
x _{High-speed access}
– Military: 25/35/55ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/20/25/35/55ns (max.)
x _{Low-power operation}
– IDT7007S
Active: 850mW (typ.)
Standby: 5mW (typ.)
– IDT7007L
Active: 850mW (typ.)
Standby: 1mW (typ.)
x _{IDT7007 easily expands data bus width to 16 bits or more}
using the Master/Slave select when cascading more than
one device
x _{M/S = H for BUSY output flag on Master,}
M/S = L for BUSY input on Slave
x _{Interrupt Flag}
x _{On-chip port arbitration logic}
x _{Full on-chip hardware support of semaphore signaling}
between ports
x _{Fully asynchronous operation from either port}
x _{TTL-compatible, single 5V (±10%) power supply}
x _{Available in 68-pin PGA and PLCC and a 80-pin TQFP}
x _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL^(1,2)
A14L
A0L
I/O
Control
I/O
Control
Address
Decoder
15
CEL
OEL
R/WL
MEMORY
ARRAY
15
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL⁽²⁾
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
1
Address
Decoder
CER
OER
R/WR
I/O0R-I/O7R
BUSYR^(1,2)
A14R
A0R
SEMR
INTR⁽²⁾
2940 drw 01
JUNE 1999
DSC 2940/8