IDT7006SL Datasheet, PDF (1/20 Pages) Integrated Device Technology – HIGH-SPEED HIGH-SPEED STATIC RAM

HIGH-SPEED
16K x 8 DUAL-PORT
STATIC RAM
IDT7006S/L
Features
◆ _{True Dual-Ported memory cells which allow simultaneous}
reads of the same memory location
◆ _{High-speed access}
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
◆ _{Low-power operation}
– IDT7006S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7006L
Active: 700mW (typ.)
Standby: 1mW (typ.)
◆ _{IDT7006 easily expands data bus width to 16 bits or more}
using the Master/Slave select when cascading more than
one device
Functional Block Diagram
OEL
CEL
R/WL
◆ _{M/S = H for BUSY output flag on Master,}
M/S = L for BUSY input on Slave
◆ _{Busy and Interrupt Flags}
◆ _{On-chip port arbitration logic}
◆ _{Full on-chip hardware support of semaphore signaling}
between ports
◆ _{Fully asynchronous operation from either port}
◆ _{Devices are capable of withstanding greater than 2001V}
electrostatic discharge
◆ _{Battery backup operation—2V data retention}
◆ _{TTL-compatible, single 5V (±10%) power supply}
◆ _{Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin}
TQFP
◆ _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
◆ _{Green parts available, see ordering information}
OER
CER
R/WR
I/O0L- I/O7L
BUSYL^(1,2)
A13L
A0L
I/O
Control
I/O
Control
Address
Decoder
14
CEL
OEL
R/WL
MEMORY
ARRAY
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL⁽²⁾
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
©2008 Integrated Device Technology, Inc.
M/S
1
Address
Decoder
CER
OER
R/WR
I/O0R-I/O7R
BUSYR^(1,2)
A13R
A0R
SEMR
INTR⁽²⁾
2739 drw 01
OCTOBER 2008
DSC- 2739/16