IDT6168SA Datasheet, PDF (1/9 Pages) Integrated Device Technology – CMOS STATIC RAM 16K (4K x 4-BIT)

CMOS Static RAM
16K (4K x 4-Bit)
IDT6168SA
IDT6168LA
Features
x _{High-speed (equal access and cycle time)}
– Military: 25/45ns (max.)
– Industrial: 25ns (max.)
– Commercial: 15/20/25ns (max.)
x _{Low power consumption}
x _{Battery backup operation—2V data retention voltage}
(IDT6168LA only)
x _{Available in high-density 20-pin ceramic or plastic DIP and}
20-pin leadless chip carrier (LCC)
x _{Produced with advanced CMOS high-performance}
technology
x _{CMOS process virtually eliminates alpha particle}
soft-error rates
x _{Bidirectional data input and output}
x _{Military product compliant to MIL-STD-883, Class B}
Description
The IDT6168 is a 16,384-bit high-speed static RAM organized
as 4K x 4. It is fabricated using lDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective approach for
high-speed memory applications.
Access times as fast 15ns are available. The circuit also offers a
reduced power standby mode. When CS goes HIGH, the circuit will
automatically go to, and remain in, a standby mode as long as CS remains
HIGH. This capability provides significant system-level power and cooling
savings. The low-power (LA) version also offers a battery backup data
retention capability where the circuit typically consumes only 1µW
operating off a 2V battery. All inputs and outputs of the IDT6168 are
TTL-compatible and operate from a single 5V supply.
The IDT6168 is packaged in either a space saving 20-pin, 300-mil
ceramic or plastic DIP or a 20-pin LCC providing high board-level
packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
Functional Block Diagram
A0
ADDRESS
DECODER
16,384-BIT
MEMORY ARRAY
VCC
GND
A11
I/O0
I/O CONTROL
I/O1
INPUT
DATA
I/O2
CONTROL
I/O3
,
CS
WE
1
©2000 Integrated Device Technology, Inc.
3090 drw 01
FEBRUARY 2001
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