IDT61298SA_07 Datasheet, PDF (1/8 Pages) Integrated Device Technology – CMOS Static RAM 256K (64K x 4-Bit)

CMOS Static RAM
256K (64K x 4-Bit)
IDT61298SA/TTSA
Features
◆ _{64K x 4 high-speed static RAM}
◆ _{Fast Output Enable (OE) pin available for added system}
flexibility
◆ _{High speed (equal access and cycle times)}
– Commercial: 12/15 ns (max.)
◆ _{JEDEC standard pinout}
◆ _{300 mil 28-pin SOJ}
◆ _{Produced with advanced CMOS technology}
◆ _{Bidirectional data inputs and outputs}
◆ _{Inputs/Outputs TTL-compatible}
◆ _{Three-state outputs}
◆ _{Military product compliant to MIL-STD-883, Class B}
Description
The lDT61298SA is a 262,144-bit high-speed static RAM organized
as 64K x 4. It is fabricated using IDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective approach for
memory intensive applications.
The IDT61298SA features two memory control functions: Chip Select
(CS) and Output Enable (OE). These two functions greatly enhance the
IDT61298SA's overall flexibility in high-speed memory applications.
Access times as fast as 12ns are available. The IDT61298SA offers
a reduced power standby mode, ISB1, which enables the designer to
considerably reduce device power requirements. This capability signifi-
cantly decreases system power and cooling levels, while greatly enhanc-
ing system reliability.
All inputs and outputs are TTL-compatible and the device operates from
a single 5V supply. Fully static asynchronous circuitry, along with matching
access and cycle times, favor the simplified system design approach.
The IDT61298SA is packaged in a 300 mil, 28-pin SOJ, providing
improved board-level packing densities.
Functional Block Diagram
A0
D
E
C
O
D
E
R
A15
262,144-BIT
MEMORY ARRAY
VCC
GND
I/O0
I/O CONTROL
I/O1
INPUT
DATA
I/O2
CONTROL
I/O3
,
CS
WE
OE
©2007 Integrated Device Technology, Inc.
2971 drw 01
FEBRUARY 2007
1
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