IDT6116SA Datasheet, PDF (1/11 Pages) Integrated Device Technology – CMOS STATIC RAM 16K (2K x 8 BIT)

CMOS Static RAM
16K (2K x 8-Bit)
IDT6116SA
IDT6116LA
Features
x _{High-speed access and chip select times}
– Military: 20/25/35/45/55/70/90/120/150ns (max.)
– Industrial: 20/25/35/45ns (max.)
– Commercial: 15/20/25/35/45ns (max.)
x _{Low-power consumption}
x _{Battery backup operation}
– 2V data retention voltage (LA version only)
x _{Produced with advanced CMOS high-performance}
technology
x _{CMOS process virtually eliminates alpha particle soft-error}
rates
x _{Input and output directly TTL-compatible}
x _{Static operation: no clocks or refresh required}
x _{Available in ceramic and plastic 24-pin DIP, 24-pin Thin Dip,}
24-pin SOIC and 24-pin SOJ
x _{Military product compliant to MIL-STD-833, Class B}
Description
The IDT6116SA/LA is a 16,384-bit high-speed static RAM
organized as 2K x 8. It is fabricated using IDT's high-performance,
high-reliability CMOS technology.
Access times as fast as 15ns are available. The circuit also offers a
reduced power standby mode. When CS goes HIGH, the circuit will
automatically go to, and remain in, a standby power mode, as long
as CS remains HIGH. This capability provides significant system level
power and cooling savings. The low-power (LA) version also offers a
battery backup data retention capability where the circuit typically
consumes only 1µW to 4µW operating off a 2V battery.
All inputs and outputs of the IDT6116SA/LA are TTL-compatible. Fully
static asynchronous circuitry is used, requiring no clocks or refreshing
for operation.
The IDT6116SA/LA is packaged in 24-pin 600 and 300 mil plastic or
ceramic DIP, 24-lead gull-wing SOIC, and 24-lead J-bend SOJ providing
high board-level packing densities.
Military grade product is manufactured in compliance to the latest
version of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance and
reliability.
Functional Block Diagram
A0
ADDRESS
DECODER
A 10
128 X 128
MEMORY
ARRAY
V CC
GND
I/O 0
I/O 7
CS
OE
WE
INPUT
DATA
CIRCUIT
CONTROL
CIRCUIT
I/O CONTROL
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©2000 Integrated Device Technology, Inc.
FEBRUARY 2001
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