IDT5V9955 Datasheet, PDF (1/11 Pages) Integrated Device Technology – 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W

IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
3.3V PROGRAMMABLE
SKEW DUAL PLL CLOCK
DRIVER TURBOCLOCK™ W
INDUSTRIAL TEMPERATURE RANGE
IDT5V9955
FEATURES:
• Ref input is 5V tolerant
• 8 pairs of programmable skew outputs
• Two separate A and B banks for individual control
• Low skew: 185ps same pair, 250ps same bank, 350ps both
banks
• Selectable positive or negative edge synchronization on each
bank: excellent for DSP applications
• Synchronous output enable on each bank
• Input frequency: 2MHz to 200MHz
• Output frequency: 6MHz to 200MHz
• 3-level inputs for skew and PLL range control
• 3-level inputs for feedback divide selection multiply / divide
ratios of (1-6, 8, 10, 12) / (2, 4)
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter: <100ps cycle-to-cycle
• Power-down mode on each bank
• Lock indicator on each bank
• Available in BGA package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The IDT5V9955 is a high fanout 3.3V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5V9955 has sixteen programmable skew
outputs in eight banks of 2. The two separate PLLs allow the user to
independently control A and B banks. Skew is controlled by 3-level input
signals that may be hard-wired to appropriate HIGH-MID-LOW levels.
The feedback input allows divide-by-functionality from 1 to 12 through
the use of the xDS[1:0] inputs. This provides the user with frequency
multiplication from 1 to 12 without using divided outputs for feedback.
When the xsOE pin is held low, all the xbank outputs are synchronously
enabled. However, if xsOE is held high, all the xbank outputs except x2Q0
and x2Q1 are synchronously disabled. The xLOCK is high when the
xbank PLL has achieved phase lock.
Furthermore, when xPE is held high, all the outputs are synchronized
with the positive edge of the REF clock input. When xPE is held low, all the
xbank outputs are synchronized with the negative edge of REF. The
IDT5V9955 has LVTTL outputs with 12mA balanced drive outputs.
ALOCK AFS
APE
AsOE
3
3
PLL
A1Q0
A1Q1
A2Q0
A2Q1
A3Q0
A3Q1
A4Q0
A4Q1
3
Skew
Select
3
3
Skew
Select
3
3
Skew
Select
3
Skew ³
Select
3
APD
/N
33
REF
TEST
AFB
ADS1:0
A1F1:0
BFB
BDS1:0
B1F1:0
A2F1:0
B2F1:0
A3F1:0
B3F1:0
A4F1:0
B4F1:0
BPD
/N
33
BPE
BFS
BLOCK
3
3
PLL
BsOE
3
Skew
Select
3
3
Skew
Select
3
3
Skew
Select
3
3
Skew
Select
3
B1Q0
B1Q1
B2Q0
B2Q1
B3Q0
B3Q1
B4Q0
B4Q1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c 2002 Integrated Device Technology, Inc.
JUNE 2002
DSC 5974/9