IDT5V995 Datasheet, PDF (1/10 Pages) Integrated Device Technology – 3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK

IDT5V995
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK™ II
INDUSTRIAL TEMPERATURE RANGE
IDT5V995
FEATURES:
• Ref input is 5V tolerant
• 4 pairs of programmable skew outputs
• Low skew: 185ps same pair, 250ps all outputs
• Selectable positive or negative edge synchronization:
Excellent for DSP applications
• Synchronous output enable
• Input frequency: 2MHz to 200MHz
• Output frequency: 6MHz to 200MHz
• 3-level inputs for skew and PLL range control
• 3-level inputs for feedback divide selection multiply / divide
ratios of (1-6, 8, 10, 12) / (2, 4)
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter: <100ps cycle-to-cycle
• Power-down mode
• Lock indicator
• Available in TQFP package
DESCRIPTION:
The IDT5V995 is a high fanout 3.3V PLL based clock driver intended for
high performance computing and data-communications applications. A key
feature of the programmable skew is the ability of outputs to lead or lag the
REF input signal. The IDT5V995 has eight programmable skew outputs in
four banks of 2. Skew is controlled by 3-level input signals that may be hard-
wired to appropriate HIGH-MID-LOW levels.
The feedback input allows divide-by-functionality from 1 to 12 through the
use of the DS[1:0] inputs. This provides the user with frequency
multiplication from 1 to 12 without using divided outputs for feedback.
When the sOE pin is held low, all the outputs are synchronously enabled.
However, if sOE is held high, all the outputs except 2Q0 and 2Q1 are
synchronously disabled. The LOCK output asserts to indicate when Phase
Lock has been achieved.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF. The IDT5V995 has
LVTTL outputs with 12mA balanced drive outputs.
FUNCTIONAL BLOCK DIAGRAM
PD
REF
FB
DS1:0
1F1:0
/N
3
3
PE TEST FS LOCK
sOE
3
3
PLL
3
Skew
S e le c t
3
1Q0
1Q1
2F1:0
3
Skew
S e le c t
3
2Q0
2Q1
3F1:0
3
Skew
S e le c t
3
3Q0
3Q1
4F1:0
3
Skew
S e le c t
3
4Q0
4Q1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c 2002 Integrated Device Technology, Inc.
FEBRUARY 2002
DSC 5851/6