IDT5V9352 Datasheet, PDF (1/10 Pages) Integrated Device Technology – 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
3.3V/2.5V PHASE-LOCK
LOOP CLOCK DRIVER
ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
IDT5V9352
FEATURES:
• Phase-lock loop clock distribution for high performance clock
tree applications
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Operates at 3.3V/2.5V VCC
• Spread Spectrum Compatible
• Operating frequency up to 200MHz
• Compatible with Motorola MPC9352
• Available in 32-pin TQFP package
DESCRIPTION:
The 5V9352 is a low-skew, low-jitter, phase-lock loop (PLL) clock driver
targeted for high performance clock tree applications. It uses a PLL to
precisely align, in both frequency and phase. The 5V9352 operates at 2.5V
and 3.3V.
The 5V9352 features three banks of individually configurable outputs.
The banks are configured with five, four, and two outputs. The internal
divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1, and 3:2:1.
The output frequency relationship is controlled by the fSEL frequency
control pins. The fSEL pins, as well as other inputs, are LVCMOS/LVTTL
compatible inputs
Unlike many products containing PLLs, the 5V9352 does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the 5V9352 requires a stabilization
time to achieve phase lock of the feedback signal to the reference signal.
This stabilization time is required, following power up and application of a
fixed-frequency, fixed-phase signal at REFCLK, as well as following any
changes to the PLL reference or feedback signals. The PLL can be
bypassed for test purposes by setting the PLL_EN to high.
The 5V9352 is available in Industrial temperature range (-40°C to
+85°C).
FUNCTIONAL BLOCK DIAGRAM
REFCLK
REF
CCLK
1
÷2 ¹
÷6
VCO
PLL
0
0
÷4
FBIN
FB
÷2
BANK A
QA0
1
QA1
0
QA2
QA3
PLL_En
QA4
VCO_SEL
fSELA
BANK B
QB0
1
QB1
0
QB2
fSELB
fSELC
QB3
BANK C
1
QC0
0
QC1
MR/OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c 2003 Integrated Device Technology, Inc.
AUGUST 2003
DSC 5973/18