IDT5V9351 Datasheet, PDF (1/10 Pages) Integrated Device Technology – LOW VOLTAGE PLL CLOCK DRIVER

IDT5V9351
LOW VOLTAGE PLL CLOCK DRIVER
LOW VOLTAGE PLL
CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
IDT5V9351
FEATURES:
• Fully integrated PLL
• Output frequency up to 200MHz
• 2.5V and 3.3V Compatible
• Compatible with PowerPC™, Intel, and high performance RISC
microprocessors
• Output frequency configurable
• Cycle-to-cycle jitter max. 22ps RMS
• Compatible with MPC9351
• Available in TQFP package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT5V9351 is a high performance, zero delay, low skew, phase-lock
loop (PLL) clock driver. It has four banks of configurable outputs. The
IDT5V9351 uses a differential PECL reference input and an external feedback
input. These features allow the IDT5V9351 to be used as a zero delay, low
skew fan-out buffer. REF_SEL allows selection between PECL input or TCLK,
a CMOS clock driver input.
If PLL_EN is set to low and REF_SEL to high, it will bypass the PLL. By doing
so, the IDT5V9351 will be in clock buffer mode. Any clock applied to TCLK will
be divided down to four output banks.
When PLL_EN is set high, PLL is enabled. Any clock applied to TCLK will
be clocked in both phase and frequency to FBIN. PECL clock is activated by
setting REF_SEL to low.
PECL_CLK
PECL_CLK
tCLK
(pullup)
(pulldown)
0
REF
1
0
÷2
1
÷4
REF_SEL
(pulldown)
PLL
÷8
FBIN
(pulldown)
FB
200 - 400MHz
PLL_En
(pullup)
fSELA
fSELB
fSELC
fSELD
(pulldown)
(pulldown)
(pulldown)
(pulldown)
(pulldown)
OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2003 Integrated Device Technology, Inc.
0
D
Q
QA
1
0
D
Q
QB
1
0
D
Q
1
0
D
Q
1
QC0
QC1
QD0
QD1
QD2
QD3
QD4
MARCH 2003
DSC-5972/16