IDT5T93GL061 Datasheet, PDF (1/14 Pages) Integrated Device Technology – 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER™ II

IDT5T93GL061
2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II
2.5V LVDS 1:6 GLITCHLESS
CLOCK BUFFER
TERABUFFER™ II
INDUSTRIAL TEMPERATURE RANGE
IDT5T93GL061
FEATURES:
• Guaranteed Low Skew < 50ps (max)
• Very low duty cycle distortion < 100ps (max)
• High speed propagation delay < 2.2ns (max)
• Up to 450MHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input interface
• Selectable differential inputs to six LVDS outputs
• Power-down mode
• 2.5V VDD
• Available in TQFP package
APPLICATIONS:
• Clock distribution
DESCRIPTION:
The IDT5T93GL061 2.5V differential clock buffer is a user-selectable
differential input to six LVDS outputs . The fanout from a differential input to six
LVDS outputs reduces loading on the preceding driver and provides an efficient
clock distribution network. The IDT5T93GL061 can act as a translator from a
differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS
input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be
used to translate to LVDS outputs. The redundant input capability allows for a
glitchless change-over from a primary clock source to a secondary clock source
up to 450MHz. Selectable inputs are controlled by SEL. During the switchover,
the output will disable low for up to three clock cycles of the previously-selected
input clock. The outputs will remain low for up to three clock cycles of the newly-
selected clock, after which the outputs will start from the newly-selected input.
A FSEL pin has been implemented to control the switchover in cases where a
clock source is absent or is driven to DC levels below the minimum specifications.
The IDT5T93GL061 outputs can be asynchronously enabled/disabled.
When disabled, the outputs will drive to the value selected by the GL pin. Multiple
power and grounds reduce noise.
FUNCTIONAL BLOCK DIAGRAM
GL
G
PD
A1
1
A1
A2
0
A2
SEL
FSEL
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2007 Integrated Device Technology, Inc.
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
JANUARY 2007
DSC 6740/7