IDT5T93GL02 Datasheet, PDF (1/14 Pages) Integrated Device Technology – 2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER™ II

IDT5T93GL02
2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER II
2.5V LVDS 1:2 GLITCHLESS
CLOCK BUFFER
TERABUFFER™ II
INDUSTRIAL TEMPERATURE RANGE
IDT5T93GL02
FEATURES:
• Guaranteed Low Skew < 50ps (max)
• Very low duty cycle distortion < 100ps (max)
• High speed propagation delay < 2.2ns (max)
• Up to 450MHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input interface
• Selectable differential inputs to two LVDS outputs
• Power-down mode
• 2.5V VDD
• Available in TSSOP package
APPLICATIONS:
• Clock distribution
DESCRIPTION:
The IDT5T93GL02 2.5V differential clock buffer is a user-selectable differ-
ential input to two LVDS outputs . The fanout from a differential input to two LVDS
outputs reduces loading on the preceding driver and provides an efficient clock
distribution network. The IDT5T93GL02 can act as a translator from a differential
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to
translate to LVDS outputs. The redundant input capability allows for a glitchless
change-over from a primary clock source to a secondary clock source up to
450MHz. Selectable inputs are controlled by SEL. During the switchover, the
output will disable low for up to three clock cycles of the previously-selected input
clock. The outputs will remain low for up to three clock cycles of the newly-
selected clock, after which the outputs will start from the newly-selected input.
A FSEL pin has been implemented to control the switchover in cases where a
clock source is absent or is driven to DC levels below the minimum specifications.
The IDT5T93GL02 outputs can be asynchronously enabled/disabled.
When disabled, the outputs will drive to the value selected by the GL pin. Multiple
power and grounds reduce noise.
FUNCTIONAL BLOCK DIAGRAM
GL
G
OUTPUT
Q1
CONTROL
Q1
PD
OUTPUT
Q2
CONTROL
Q2
A1
1
A1
A2
0
A2
SEL
FSEL
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2007 Integrated Device Technology, Inc.
JANUARY 2007
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