IDT5T9316 Datasheet, PDF (1/12 Pages) Integrated Device Technology – 2.5V LVDS 1:16 CLOCK BUFFER TERABUFFER II

IDT5T9316
2.5V LVDS 1:16 CLOCK BUFFER TERABUFFER II
2.5V LVDS 1:16
CLOCK BUFFER
TERABUFFER™ II
INDUSTRIAL TEMPERATURE RANGE
IDT5T9316
FEATURES:
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 125ps (max)
• High speed propagation delay < 1.75ns (max)
• Up to 1GHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input interface
• Selectable differential inputs to sixteen LVDS outputs
• Power-down mode
• 2.5V VDD
• Available in VFQFPN package
DESCRIPTION:
The IDT5T9316 2.5V differential clock buffer is a user-selectable differential
input to sixteen LVDS outputs. The fanout from a differential input to sixteen LVDS
outputs reduces loading on the preceding driver and provides an efficient clock
distribution network. The IDT5T9316 can act as a translator from a differential
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to
translate to LVDS outputs. The redundant input capability allows for an
asynchronous change-over from a primary clock source to a secondary clock
source. Selectable reference inputs are controlled by SEL.
The IDT5T9316 outputs can be asynchronously enabled/disabled. When
disabled, the outputs will drive to the value selected by the GL pin. Multiple power
and grounds reduce noise.
APPLICATIONS:
• Clock distribution
FUNCTIONAL BLOCK DIAGRAM
GL
G1
PD
A1
1
A1
A2
0
A2
SEL
G2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
OUTPUT
CONTROL
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CONTROL
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
Q10
Q10
Q11
Q11
Q12
Q12
Q13
Q13
Q14
Q14
Q15
Q15
Q16
Q16
MARCH 2004
DSC-6174/14