IDT5T9306 Datasheet, PDF (1/13 Pages) Integrated Device Technology – 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II

2.5V LVDS 1:6 CLOCK BUFFER
TERABUFFER™ II
IDT5T9306
FEATURES:
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 125ps (max)
• High speed propagation delay < 1.75ns (max)
• Additive phase jitter, RMS 0.159ps (typical) @ 125MHz
• Up to 1GHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input interface
• Selectable differential inputs to six LVDS outputs
• Power-down mode
• 2.5V VDD
• Available in VFQFPN package
DESCRIPTION:
The IDT5T9306 2.5V differential clock buffer is a user-selectable differential
input to six LVDS outputs. The fanout from a differential input to six LVDS outputs
reduces loading on the preceding driver and provides an efficient clock
distribution network. The IDT5T9306 can act as a translator from a differential
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to
translate to LVDS outputs. The redundant input capability allows for an
asynchronous change-over from a primary clock source to a secondary clock
source. Selectable reference inputs are controlled by SEL.
The IDT5T9306 outputs can be asynchronously enabled/disabled. When
disabled, the outputs will drive to the value selected by the GL pin. Multiple power
and grounds reduce noise.
APPLICATIONS:
• Clock distribution
FUNCTIONAL BLOCK DIAGRAM
GL
G
OUTPUT
Q1
CONTROL
Q1
PD
OUTPUT
Q2
CONTROL
Q2
A1
1
A1
OUTPUT
Q3
CONTROL
Q3
A2
0
OUTPUT
Q4
A2
CONTROL
Q4
OUTPUT
Q5
SEL
CONTROL
Q5
OUTPUT
Q6
CONTROL
Q6
IDT^™ / ICS^™ LVDS CLOCK BUFFER TERABUFFER™ II
1
IDT5T9306 REV. A OCTOBER 23, 2007