IDT5T915 Datasheet, PDF (1/19 Pages) Integrated Device Technology – 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER

IDT5T915
2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER
2.5V DIFFERENTIAL
1:5 CLOCK BUFFER
TERABUFFER™
INDUSTRIAL TEMPERATURE RANGE
IDT5T915
FEATURES:
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 300ps (max)
• High speed propagation delay < 2ns (max)
• Up to 250MHz operation
• Very low CMOS power levels
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input
interface
• Selectable differential or single-ended inputs and five differen-
tial outputs
• 2.5V VDD
• Available in TSSOP package
APPLICATIONS:
• Clock and signal distribution
FUNCTIONAL BLOCK DIAGRAM
TxS
GL
G(+)
DESCRIPTION:
The IDT5T915 2.5V differential (DDR) clock buffer is a user-selectable
single-ended or differential input to five differential outputs built on advanced
metal CMOS technology. The differential clock buffer fanout from a single or
differential input to five differential or single-ended outputs reduces loading on
the preceding driver and provides an efficient clock distribution network. The
IDT5T915 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V
LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL,
1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input
signals that may be hard-wired to appropriate high-mid-low levels.
The IDT5T915 true or complementary outputs can be asynchronously
enabled/disabled. Multiple power and grounds reduce noise.
OUTPUT
CONTROL
Q1
OUTPUT
CONTROL
Q1
RxS
A
A/VREF
G(-)
OUTPUT
CONTROL
Q2
OUTPUT
CONTROL
Q2
OUTPUT
CONTROL
Q3
OUTPUT
CONTROL
Q3
OUTPUT
CONTROL
Q4
OUTPUT
CONTROL
Q4
OUTPUT
CONTROL
Q5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2003 Integrated Device Technology, Inc.
OUTPUT
CONTROL
1
Q5
FEBRUARY 2003
DSC-5893/21